The invention concerns an electronic apparatus and method for receiving noisy signals.
Many Electronic Apparatuses for Receiving Noisy Signals (i.e.xe2x80x94EARNS), such as, but not limited to a mobile car radio, include one or more filters and/or and one or more equalizers. Some filters or equalizers output signals can be in a form referred to in the art as xe2x80x9chard dataxe2x80x9d or xe2x80x9csoft dataxe2x80x9d. Methods and devices for producing hard data and soft data are well known in the art: for example, a Viterby Algorithm method, a Matched Filter, a Maximum Likelihood Sequence Estimator (i.e.xe2x80x94MLSE), and Inter Symbol Interference (i.e. xe2x80x94ISI) cancellation method. The following references give a description of some prior art methods and devices for producing hard data and/or soft data: xe2x80x9cSoft-Output MLSE Equalization Methods for the Mobile Radio Channelxe2x80x9d, by J. Nowack, D. Borth and P. Rasky; xe2x80x9cTCM on Frequency-Selective Fading Channels: a comparison of Soft-Output Probabilistic Equalizersxe2x80x9d, by P. Hoeher, Conf. Ref. GLOBECOM""90, pg. 401.1-401.1.6, December 1990, published by IEEE; xe2x80x9cThe Viterbi Algorithmxe2x80x9d, by G. D. Forney Jr., Proceedings of the IEEE, vol. 61, No. 3, pg. 258-278, March 1973; xe2x80x9cA Viterby Algorithm with Soft-Decision Outputs and its Applicationsxe2x80x9d, by J. Hagenauer and P. Hoeher, Conf. Ref. GLOBECOM""89, Dallas, Tex., Vol. 3, pg. 47.1.1-47.1.7, November 1989; xe2x80x9cAdaptive Maximum Likelihood Receiver for Carrier-Modulated Data Transmission Systemsxe2x80x9d, by G. Ungerboeck,IEEE Transactions on Communications. COM-22, pg. 624-636, May 1974; U.S. Pat. No. 5,497,383 May 1996, J. Thome, A. Arora, N. Vinggaard, xe2x80x9cError Detector Circuit for Receiver Operative to Receive Discretely-Encoded Signalsxe2x80x9d.
Hard data is usually represented by a single bit, and soft data is usually represented by several bits. Hard data contains a decision about a signal that was received by the EARNS and soft data contains data about reliability information. Soft data concerns both the received signal and the channel behavior.
Hard data can be the output signal of a Viterbi Algorithm unit (i.e.xe2x80x94Viterbi unit) and soft data can be the output signal of a matched filter or a soft decision generator (see FIG. 1). A soft decision generator can also output a hard data signal (see FIG. 2). The usage of both hard data and soft data increases the EARNS performance.
In the prior art, EARNS usually dealt with soft data and hard data in one of the following ways:
a. Storing hard data and soft data in separate data banks (as shown in FIG. 2).
b. Outputting just soft data, and using soft data Most Significant Bit (MSB) as hard data (as shown in FIG. 1).
The main disadvantage of the first arrangement is a complication of software and hardware, increased number of memory banks, increased number of Direct Memory Access (DMA) channels and controllers, and increased core access operation used to process the two kinds of data. The main disadvantage of the second arrangement is a decrease in EARNS performance, due to the fact that soft data MSB does not always equals the hard data.
For the above mentioned reasons and other reasons, there continues to be a need for an improved EARNS.
FIG. 1 shows typical prior art portion 8 of an EARNS, implementing an ISI-Cancellation method. Portion 8 has soft decision generator 30, having input 32 and output 34; delay element 40, having input 42 and output 44; adder 50 having input 52, inverting input 54 and output 56, and Maximum Likelihood Sequence Estimator (i.e.xe2x80x94MLSE) 10. MLSE 10 includes Matched Filter (i.e.xe2x80x94MF) 12, having input 14 and output 16 and Viterbi unit (i.e.xe2x80x94VA) 20, having input 22 and output 24. Output 16 of MF 12 is coupled to input 22 of VA 20 and to input 42 of delay element 40. Output 24 of VA 20 is coupled to input 32 of soft decision generator 30. Output 34 of soft decision generator 30 is coupled to inverting input 54 of adder 50. Output 44 of delay element 40 is coupled to input 52 of adder 50. Output signal appearing on output 24 of VA 24 is hard data. Output signals appearing on outputs 16, 34, 44, 56 of MF 12, soft decision generator 30, delay element 40 and adder 50 respectively, are soft data.
Portion 8 has no hard data signal output. The MSB of soft data is used as the hard data signal. The main disadvantage of this arrangement is a decreased performance.
FIG.2 is a schematic description of portion 108 of a prior art EARNS implementing an ISI-Cancellation method. Portion 108 has Maximum Likelihood Sequence Estimator (i.e.xe2x80x94MLSE) 110, wherein MLSE 110 has a Matched Filter (i.e.xe2x80x94MF) 112, having input 114 and output 116 and a Viterbi Algorithm unit (i.e.xe2x80x94VA) 120, having input 122 and output 124. Soft decision generator 130 has inputs 132, 137 and outputs 134,136,138. Delay element 140, has input 142 and output 144. Adder 150 has inputs 152, 157, inverting input 154 and outputs 156, 158. Hard data controller 160, has inputs 162, 165 and outputs 164, 167. Hard data memory bank 170, has inputs 172, 174 and outputs 175 and 176. Soft data controller 180, has inputs 182, 185 and outputs 187,184, and soft data memory bank 190, has inputs 192, 194 and outputs 195 and 196.
Output 116 of MF 112 is coupled to input 122 of VA 120 and to input 142 of delay element 140. Output 124 of VA 120 is coupled to input 132 of soft decision generator 130. Output 144 of delay element 140 is coupled to input 152 of adder 150. Output 134 of soft decision generator 130 is coupled to input 174 of hard data memory bank 170. Output 138 of soft decision generator 130 is coupled to input 162 of hard data controller 160. Output 136 of soft decision generator 130 is coupled to inverting input 154 of adder 150. Output 164 of hard data controller 160 is coupled to input 172 of hard data memory bank 170. Output 156 of adder 150 is coupled to input 192 of soft data memory bank 190. Output 158 of adder 150 is coupled to input 182 of soft data controller 180. Output 184 of soft data controller 180 is coupled to input 194 of soft data memory bank 190. Output 167 of hard data controller 160 is coupled to input 137 of soft decision generator 130. Output 175 of hard data memory bank 170 is coupled to input 165 of hard data controller 160.
Soft data controller 180 handles data transfer from adder 150 to soft data memory bank 170 in a manner well known in the prior art. For example, adder 150 sends to soft data controller 180, via output 158 and input 182 respectively, a signal indicating that it has updated soft data. Soft data controller sends a xe2x80x98WRITExe2x80x99 signal to soft data memory bank 190, causing the updated data within adder 150 to be written to soft data memory bank. Soft data controller can also determine in which address of soft data memory 190 to write the updated soft data.
Hard data controller 160 handles data transfer from soft decision generator 130 to hard data memory bank 170, in a manner well known in the prior art.
Hard data controller 160 and soft data controller 180 can be implemented by one or more Direct Memory Access (DMA) units, but can also be implemented by one or more interrupt generating units coupled to a processor. The main disadvantage of this arrangement is a complication of software and hardware, increased number of memory banks, increased number of Direct Memory Access (DMA) channels and controllers, and increased core access operation used to process the two kinds of data.